Elaborate Refresh: A Fine Granularity Retention Management for Deep Submicron DRAMs

• Published in: IEEE transactions on computers Vol. 67; no. 10; pp. 1403 - 1415
• Main Authors: Seol, Hoseok, Shin, Wongyu, Jang, Jaemin, Choi, Jungwhan, Lee, Hakseung, Kim, Lee-Sup
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.10.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Capacitors; DRAM; DRAM chips; dual rate refresh; Energy conservation; Energy storage; Memory management; refresh management; Retention; retention aware refresh; Sociology; Statistics; Transistors
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2018.2820052

As the DRAM cell size continues to shrink, the proportion of leaky cells is increasing. As a result, the prior approaches, called retention aware refresh, which skip unnecessary refresh operations for non-leaky cells, are unable to skip as many refresh operations as before. The large granularity of the DRAM refresh mechanism makes this problem more serious. Specifically, even when there are only a small number of leaky cells in a particular retention group, that group is classified as a leaky group. Because of that, many non-leaky cells that also belong to that group are refreshed at an unnecessarily frequent rate. Since the granularity of the retention group is larger, this inefficiency becomes huge. To solve this problem, we propose a novel retention aware refresh approach called Elaborate Refresh, to reduce the granularity of the retention group further. The key idea of the Elaborate Refresh is to store leaky row addresses per each chip, and refresh different leaky row in each chip simultaneously. By doing so, Elaborate Refresh reduces the overhead of the leaky group refresh 16 times. In addition, Elaborate Refresh stores retention information in the DRAM chip, thus saving the refresh energy, even in the self-refresh mode when the memory controller cannot control the DRAM.