Realization of vertical resistive memory (VRRAM) using cost effective 3D process

Vertical ReRAM (VRRAM) has been realized with modification of Vertical NAND (VNAND) process and architecture as a cost-effective and extensible technology for future mass data storage. Dedicated ALD/CVD deposition and wet etching processes were developed to reproduce planar ReRAM properties in VRRAM...

Full description

Saved in:
Bibliographic Details
Published in2011 International Electron Devices Meeting pp. 31.8.1 - 31.8.4
Main Authors Baek, I. G., Park, C. J., Ju, H., Seong, D. J., Ahn, H. S., Kim, J. H., Yang, M. K., Song, S. H., Kim, E. M., Park, S. O., Park, C. H., Song, C. W., Jeong, G. T., Choi, S., Kang, H. K., Chung, C.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2011
Subjects
Computer architecture
Electrodes
Helium
Resistance
Switches
Three dimensional displays
Tin
Online AccessGet full text

Cover

More Information
Summary:Vertical ReRAM (VRRAM) has been realized with modification of Vertical NAND (VNAND) process and architecture as a cost-effective and extensible technology for future mass data storage. Dedicated ALD/CVD deposition and wet etching processes were developed to reproduce planar ReRAM properties in VRRAM structure. Multi-stack of VRRAM cell layers were fabricated at the same time using ALD TaOx/barrier layer/CVD TiN cell stacks. Oxidation control without intermixing has been found very critical in the vertical ReRAM cell process.
ISBN:1457705060
9781457705069
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2011.6131654