Design and HDL Implementation of Pulse-Arrival-Time Estimation Using XGBoost Regression With Tree-Recycling Architecture
This paper presents a pulse-arrival-time (PAT) estimation scheme using Extreme Gradient Boosting (XGBoost) regression and its implementation with hardware description language (HDL). PAT is a significant metric for the estimation of pulse wave velocity (PWV) and blood pressure. We leverage morpholog...
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Published in | IEEE access Vol. 13; pp. 27596 - 27609 |
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Main Authors | , |
Format | Journal Article |
Language | English |
Published |
Piscataway
IEEE
2025
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | This paper presents a pulse-arrival-time (PAT) estimation scheme using Extreme Gradient Boosting (XGBoost) regression and its implementation with hardware description language (HDL). PAT is a significant metric for the estimation of pulse wave velocity (PWV) and blood pressure. We leverage morphological features of single photoplethysmogram (PPG) waveforms and subject-specific parameters to estimate PAT values through a decision tree ensemble regression model. XGBoost regression is adopted for PAT estimation through a comparative study conducted in software. To enable the integration of the regression model into a single chip, we propose a tree-recycling architecture for an area-efficient implementation of the decision tree ensemble model. The proposed PAT estimation has been implemented on a field-programmable gate array (FPGA, Artix7, Xilinx) for real-time verification using a dataset. Additionally, the active area of the proposed scheme in an integrated circuit was estimated after the place-and-route (PnR) procedure, resulting in an area of 1.44 mm2. We utilized the Vital Signs DataBase (VitalDB) for training and testing the proposed PAT estimation in a software-hardware co-design framework. Validation on 80 subjects yielded a determination coefficient (R2) of 0.983 in the linear regression analysis after implementing the HDL on an FPGA. |
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Bibliography: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 |
ISSN: | 2169-3536 2169-3536 |
DOI: | 10.1109/ACCESS.2025.3540440 |