In‐Memory Hamming Weight Calculation in a 1T1R Memristive Array

• Published in: Advanced electronic materials Vol. 6; no. 9
• Main Authors: Cheng, Long, Li, Jiancong, Zheng, Hao‐Xuan, Yuan, Peng, Yin, Jiahao, Yang, Ling, Luo, Qing, Li, Yi, Lv, Hangbing, Chang, Ting‐Chang, Miao, Xiangshui
• Format: Journal Article
• Language: English
• Published: 01.09.2020
• Subjects: Hamming weight; in‐memory computing; matrix accumulation; matrix multiplication accumulation; memristors
• ISSN: 2199-160X; 2199-160X
• DOI: 10.1002/aelm.202000457

In‐memory computing enabled by advanced nonvolatile memory technologies, such as memristors and memristive devices, emerges as a promising approach to accelerate certain data‐intensive algorithms, and thus outperforms the von Neumann computing in terms of processing latency and energy efficiency. In this work, an efficient method to calculate the Hamming weight (HW) of a binary string in a one‐transistor‐one‐resistor (1T1R) memristive array is proposed, which can be beneficial for various computation tasks. Specifically, the target string is converted to a voltage vector and multiplies with an “all‐1” string pre‐stored in the resistance of the row, which equals to a binary matrix multiplication or AND logic operation. The in situ stored HW calculation result is then read out through a current accumulation operation. As a proof‐of‐concept demonstration, 4 bit and 8 bit HW calculation is successfully implemented in experiment and simulation, respectively. In addition, the influence of the resistance variation on the calculation correctness is discussed. This work broadens the application range of using emerging nonvolatile memories for classical information processing in hardware level with high efficiency. An efficient Hamming weight calculation method based on binary matrix multiplication and accumulation in one‐transistor‐one‐resistor crossbar array is proposed and implemented. The three‐step in‐memory operation paradigm with high parallelism proves potential advantage over traditional central processing unit paradigm in terms of processing latency and energy efficiency, providing alternative choice for classical information processing with improved performance.