A 3-D Crossbar Architecture for Both Pipeline and Parallel Computations

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 68; no. 11; pp. 4456 - 4469
• Main Authors: Aljafar, Muayad J., Acken, John M.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 3-D circuit; Arrays; Circuits; CMOS; Computer architecture; Cryptography; Hardware; Logic arrays; Logic gates; memristor crossbar arrays; Memristors; parallel and pipeline computation; Resistance; stateful logic computation; Substrates; Three-dimensional displays
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2021.3108564

A 3D architecture made up of a CMOS layer combined with a 3D stack of bipolar memristor crossbar arrays provides an innovative approach to hardware support for utilizing the strength of CMOS combined with the strength of memristors. Memristors have been evaluated for implementing a broad spectrum of applications such as memory, computations, hardware-based security primitives, cryptography, etc., and numerous studies have shown that memristors are desirable candidates for such applications. This paper proposes a novel 3D memristive crossbar architecture (i.e., a stack of memristive crossbar arrays built on top of CMOS substrate) with a specific focus on the way of connecting the crossbar arrays to the CMOS layer. The proposed architecture is configurable and allows restructuring crossbar arrays and creating 1D arrays with adjustable sizes. The proposed architecture enables parallel and pipeline computations where data can move or be processed in planes perpendicular to the stacked crossbar arrays. In addition, the proposed architecture is scalable meaning that stacks of crossbar arrays can be connected without additional overhead. This paper shows examples of implementing a full adder, a 4-bit look-ahead carry generator, and an 8-bit multiplexer. Simulations and area, delay, and power analysis demonstrate the behavior of the proposed 3D circuit.