Design and validation through a frequency-based metric of a new countermeasure to protect nanometer ICs from side-channel attacks

• Published in: Journal of cryptographic engineering Vol. 5; no. 4; pp. 269 - 288
• Main Authors: Bongiovanni, Simone, Centurelli, Francesco, Scotti, Giuseppe, Trifiletti, Alessandro
• Format: Journal Article
• Language: English
• Published: Berlin/Heidelberg Springer Berlin Heidelberg 01.11.2015
• Subjects: Circuits and Systems; Communications Engineering; Computer Communication Networks; Computer Science; Cryptology; Data Structures and Information Theory; Networks; Operating Systems; Regular Paper; Decoupling capacitor; VLSI; Serpent S-Box; Correlation power analysis; Side-channel attacks; Fast Fourier transform
• ISSN: 2190-8508; 2190-8516
• DOI: 10.1007/s13389-015-0096-z

Electrical and capacitive mismatches are outstanding issues in modern submicron technologies, and must be considered already during the design steps. In this work, we propose a novel hardware countermeasure based on the combination of a circuit- and a system-level methodology, which helps to reduce the data dependence of the instantaneous power consumption of cryptographic circuits. Accordingly, we define a specific design methodology, which is based on a novel data encoding and on the insertion of an on-chip filter implemented through capacitances in the layout. The new countermeasure, called time-enclosed logic ( TEL ), is able to hide the data dependence in a very short time interval (in the order of 100 ps in modern submicron technologies), constraining the minimum amount of bandwidth required from the attack setup. As a second and parallel contribution, we present a novel design time metric for validating our design, named frequency energy deviation , which is based on the investigation of the deviation of the frequency patterns of the current traces. By simulating a basic cell template under unbalanced capacitive condition, we show that standard dual-rail precharge logics exhibit a resilient leakage already at lower frequencies, whereas in TEL circuits the data dependence is shifted toward high frequencies. As a case study, we designed a TEL-featured cryptographic circuit using a 65-nm technology node, without any assumption on the routing of the logic gates. Correlation power analysis attacks with a Gaussian model have been then mounted against the circuit. Simulation results show that the proposed countermeasure can help to mitigate the electrical mismatches occurring in submicron technologies, offering a promising perspective for the design of power analysis resistant circuits.