Yield Prediction for Integrated Circuits Manufacturing Through Hierarchical Bayesian Modeling of Spatial Defects

• Published in: IEEE transactions on reliability Vol. 60; no. 4; pp. 729 - 741
• Main Authors: Tao Yuan, Ramadan, S. Z., Bae, S. J.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2011; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Bayesian methods; Data models; Hierarchical bayesian model; Integrated circuit manufacture; Integrated circuit modeling; Mathematical models; Semiconductor device modeling; spatial defects; Studies; Yield estimation; yield prediction; zero-inflated models
• ISSN: 0018-9529; 1558-1721
• DOI: 10.1109/TR.2011.2161698

Accurate yield prediction to evaluate productivity, and to estimate production costs, is a critical issue in the highly competitive semiconductor industry. We propose yield models based on hierarchical Bayesian modeling of clustered spatial defects produced in integrated circuits (IC) manufacturing. We use spatial locations of the IC chips on the wafers as covariates, and develop four models based on Poisson regression, negative binomial (NB) regression, zero-inflated Poisson (ZIP) regression, and zero-inflated negative binomial (ZINB) regression. Along with the hierarchical Bayesian approaches, spatial variations of defects within one wafer as well as among different wafers are effectively incorporated in the yield models. Wafermap data obtained from an industrial collaborator are used to illustrate the proposed models. The results indicate that the Poisson regression model consistently underestimates the true yield because of extraneous Poisson variation caused by defect clustering. On the contrary, NB regression, ZIP regression, and ZINB regression models provide more reliable yield estimation and prediction in real applications.