Critical Role of Interlayer in Hf0.5Zr0.5O2 Ferroelectric FET Nonvolatile Memory Performance

• Published in: IEEE transactions on electron devices Vol. 65; no. 6; pp. 2461 - 2469
• Main Authors: Ni, Kai, Sharma, Pankaj, Zhang, Jianchi, Jerry, Matthew, Smith, Jeffery A., Tapily, Kandabara, Clark, Robert, Mahapatra, Souvik, Datta, Suman
• Format: Journal Article
• Language: English
• Published: IEEE 01.06.2018
• Subjects: Capacitors; Charge trapping; ferroelectric FET (FeFET); Hafnium oxide; Hf₀.₅Zr₀.₅O₂ (HZO); interlayer (IL); Iron; Logic gates; Nonvolatile memory; Pulse measurements; Switches
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2018.2829122

We fabricate, characterize, and establish the critical design criteria of Hf 0.5 Zr 0.5 O 2 (HZO)-based ferroelectric field effect transistor (FeFET) for nonvolatile memory application. We quantify <inline-formula> <tex-math notation="LaTeX">{V}_{\textsf {TH}} </tex-math></inline-formula> shift from electron (hole) trapping in the vicinity of ferroelectric (FE)/interlayer (IL) interface, induced by erase (program) pulse, and <inline-formula> <tex-math notation="LaTeX">{V}_{\textsf {TH}} </tex-math></inline-formula> shift from polarization switching to determine true memory window (MW). The devices exhibit extrapolated retention up to 10 years at 85 °C and endurance up to <inline-formula> <tex-math notation="LaTeX">5\times 10^{6} </tex-math></inline-formula> cycles initiated by the IL breakdown. Endurance up to 10 12 cycles of partial polarization switching is shown in metal-FE-metal capacitor, in the absence of IL. A comprehensive metal-FE-insulator-semiconductor FeFET model is developed to quantify the electric field distribution in the gate-stack, and an IL design guideline is established to markedly enhance MW, retention characteristics, and cycling endurance.