CMOS Hardening Techniques

Complementary symmetry MOS circuits have high noise immunity and low power consumption which make them particularly suitable for military and space applications. A major drawback to their use is radiation sensitivity to accumulated fluences of radiation and also to prompt radiation bursts (transient...

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Bibliographic Details
Published inIEEE transactions on nuclear science Vol. 19; no. 6; pp. 275 - 281
Main Authors Schlesier, K. M., Norris, P. E.
Format Journal Article
LanguageEnglish
Published IEEE 01.01.1972
Subjects
Aluminum oxide
Circuit noise
CMOS technology
Dielectrics
Energy consumption
Isolation technology
Photoconductivity
Radiation hardening
Silicon
Space technology
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Summary:Complementary symmetry MOS circuits have high noise immunity and low power consumption which make them particularly suitable for military and space applications. A major drawback to their use is radiation sensitivity to accumulated fluences of radiation and also to prompt radiation bursts (transient effects). A significant degree of hardening against transient effects can be achieved by building the circuits in silicon-on-sapphire. This technology provides complete dielectric isolation and reduces photocurrents in the silicon. It is shown that each device type (N and P channel) must operate under both negative and positive gate bias. Therefore, to ensure hardening against an accumulated fluence of radiation, a dielectric which is hard under both polarities of gate bias should be used. Results are presented for CMOS circuits made with Al2O3 gate insulators.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.1972.4326845