A new MoSi2/Thin poly-Si gate process technology without dielectric degradation of a gate oxide

• Published in: IEEE transactions on electron devices Vol. 31; no. 10; pp. 1432 - 1439
• Main Authors: Fukumoto, M., Shinohara, A., Okada, S., Kugimiya, K.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.10.1984; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Electronics; Exact sciences and technology; Microelectronic fabrication (materials and surfaces technology); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Ion implantation; Annealing; Solid solid reaction; Stability; Performance characteristic; Polycrystal; Oxides; Phosphorus; High temperature; Electric strength; Thin film; Insulation technology; Microelectronic fabrication; Molybdenum Silicides; Thick film; Silicon; Reliability; Deposition
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/T-ED.1984.21729

The dielectric degradation phenomena in gate oxides of MoSi 2 /thin n + poly-Si (<100 nm) gate structure which appeared after high-temperature annealing have been analyzed in detail. Analyses included obtaining the correlation between gate oxide dielectric characteristics and various factors like phosphorus concentration in poly-Si, native oxide on poly-Si, sheet resistance of MoSi 2 , and the SEM or TEM observations of textures of MoSi 2 , poly-Si, and gate oxide. From analyses, it was concluded that the local reaction of molybdenum silicide with poly-Si under the presence of a barrier, like the thick native oxide on poly-Si formed before MoSi 2 deposition, results in the damage to a gate oxide through a thin poly-Si layer during annealing. Based upon analytical results, a new MoSi 2 /thin poly-Si gate process without dielectric degradation has been developed, in which the direct MoSi 2 deposition on undoped poly-Si to suppress the native oxide growth and phosphorus implantation into MoSi 2 were introduced. The process provided a good dielectric strength of a gate oxide even to the device with a poly-Si layer as thin as 50 nm, an easy dry etching without undercutting of poly-Si, and stable device characteristics and reliabilities compatible to a conventional poly-Si gate process.