A stacked capacitor cell with a fully self-aligned contact process for high-density dynamic random access memories

• Published in: Journal of the Electrochemical Society Vol. 139; no. 8; pp. 2318 - 2322
• Main Authors: KÜSTERS, K. H, SESSELMANN, W
• Format: Conference Proceeding Journal Article
• Language: English
• Published: Pennington, NJ Electrochemical Society 01.08.1992
• Subjects: Applied sciences; Electronics; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Line contact; Breakdown voltage; Microelectronic fabrication; Random access memory(RAM); Self alignment; Dynamical storage; Selective etching; Leakage current; Capacitor; Electrical characteristic
• ISSN: 0013-4651; 1945-7111
• DOI: 10.1149/1.2221223

A new, self-aligned contact process has been developed for a stacked capacitor dynamic random access memories (DRAM) cell. The bit line contact is three-fold, self-aligned with respect to transistor gate, the field oxide, and the upper cell plate of the stacked capacitor. An oxide spacer technique is used to encapsulate the transistor gate. Etching of the overlapping bit line contact is self-aligned by a proper choice of deposited materials and etch selectivities and does not affect the oxide isolation of the transistor gate and the field oxide. In addition, the stacked capacitor cell plate is self-aligned and isolated from the bit line by a selective oxidation process. Using this technique, optimal contact window shaping and improved planarization of the interconnect dielectric isolation is simultaneously achieved. This fully self-aligned contact process allows an increase in cell capacitance by a factor of about 1.4. No electrical degradation compared to a conventional contact process has been observed. For reduction of contact resistance, a process based on Si super(+)-ion implantation with subsequent annealing has been developed.