NPN SiGe Hetero Junction Transistor Latch-Up Memory Selector

• Published in: IEEE electron device letters Vol. 44; no. 4; pp. 614 - 617
• Main Authors: Hiblot, Gaspard, Ravsher, Taras, Loo, Roger, Ramana, Bhuvaneshwari Yengula Venkata, Canvel, Yann, Vergel, Nathali Franchina, Fantini, Andrea, Sharifi, Shamin Houshmand, Bazzazian, Nina, Ayyad, Mustafa, Merkulov, Alex, Kar, Gouri Sankar, Couet, Sebastien
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Dynamic models; Electrical junctions; Epitaxial growth; Germanium; HBT; Latch-up; Memory devices; NPN; Phosphorus; Selector; Semiconductor device modeling; Semiconductor process modeling; SiGe; Silicon; Silicon germanides; Silicon germanium; Transistors
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2023.3242302

NPN latch-up memory selector devices featuring SiGe hetero-junctions are fabricated and measured electrically. 25% Ge is introduced into the floating base layer by epitaxy. The performance of this device is compared against an implanted Si stack. It is observed that the addition of 25% Ge in the floating base layer of these latch-up selector devices boosts the non-linearity by more than <inline-formula> <tex-math notation="LaTeX">\times {100} </tex-math></inline-formula> and enables abrupt latch-up below 2V. TCAD simulations comparing drift-diffusion and hydro-dynamic models are used to validate our understanding of the device.