A VLSI analog pipeline read-out for electrode segmented ionization chambers
We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.
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Published in | Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment Vol. 426; no. 2; pp. 544 - 550 |
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Main Authors | , , , , , , , , , |
Format | Journal Article |
Language | English |
Published |
Elsevier B.V
01.05.1999
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Subjects | |
Online Access | Get full text |
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Summary: | We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing. |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 0168-9002 1872-9576 |
DOI: | 10.1016/S0168-9002(99)00022-4 |