Multiphase digital pulsewidth modulator
This letter describes a digital pulsewidth modulator that enables the generation of a large, adjustable number of pulsewidth modulated (PWM) outputs of programmable duty cycle and dead time, yet requiring just a small, fixed architecture. The design achieves a resolution of 255 ps using a composite...
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Published in | IEEE transactions on power electronics Vol. 21; no. 3; pp. 842 - 846 |
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Main Authors | , , , |
Format | Journal Article |
Language | English |
Published |
New York, NY
IEEE
01.05.2006
Institute of Electrical and Electronics Engineers |
Subjects | |
Online Access | Get full text |
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Summary: | This letter describes a digital pulsewidth modulator that enables the generation of a large, adjustable number of pulsewidth modulated (PWM) outputs of programmable duty cycle and dead time, yet requiring just a small, fixed architecture. The design achieves a resolution of 255 ps using a composite PWM strategy that also minimizes clock frequency and area. It provides a practical solution to the problem of efficiently generating multiple high-resolution gate-drive signals and is particularly suited to the next generation of synchronously switched multiphase voltage regulator modules |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 0885-8993 1941-0107 |
DOI: | 10.1109/TPEL.2006.875569 |