Multi-input volistor logic XNOR gates

• Published in: International journal of parallel, emergent and distributed systems Vol. 35; no. 4; pp. 423 - 432
• Main Authors: Aljafar, Muayad J., Perkowski, Marek A., Acken, John M.
• Format: Journal Article
• Language: English
• Published: Abingdon Taylor & Francis 03.07.2020; Taylor & Francis Ltd
• Subjects: Block diagrams; Circuit diagrams; CMOS; Computer simulation; ESOP (Exclusive-OR Sum-of-Products); Gates (circuits); hybrid CMOS-memristive circuits; Logic; Logic circuits; Mathematical analysis; Memristors; Power consumption; Power management; rectifying memristors; stateful logic; Switches; volistor logic; XNOR logic
• ISSN: 1744-5760; 1744-5779
• DOI: 10.1080/17445760.2019.1649403

A novel approach utilising the emerging memristor technology is introduced for realising a 2-input primitive XNOR gate. This gate enables in-memory computing and is used as a building block of multi-input XNOR gates. The XNOR gate is realised with eight memristors of two crossbar arrays. The average power consumption of an 8-input XNOR gate is calculated and compared with its counterpart realised with CMOS technology - the XNOR gate consumes less power. ESOP realisation can be directly implemented with XNOR gates. Our simulation results and comparisons show the benefit of the proposed XNOR gate in terms of delay, area, and power. Volistor logic XNOR gate. (a) Circuit diagram of two-input volistor logic XNOR gate. Input voltages are applied to memristors S 1 and S 2 through horizontal wires W in1 and W in2 , and the output which is logical AND of states S 1 and S 2 is calculated by applying V READ to vertical wire W XNOR . (b) Block diagram of two-input volistor logic gate. (c) A multi-input volistor logic XNOR gate can be implemented by connecting two XNOR gates though CMOS switches.