Research and Design of Asynchronous FIFO Based on FPGA
In this article, a design method of asynchronous FIFO memory based on FPGA is put forward. With FPGA as the core controller, We adopt Verilog HDL and top-down design method to build a top-level module design and also analyze the mark logic of asynchronous FIFO and the elimination of semi-stable stat...
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Published in | Applied Mechanics and Materials Vol. 644-650; pp. 3440 - 3444 |
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Main Authors | , , , , |
Format | Journal Article |
Language | English |
Published |
Zurich
Trans Tech Publications Ltd
01.09.2014
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Subjects | |
Online Access | Get full text |
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Summary: | In this article, a design method of asynchronous FIFO memory based on FPGA is put forward. With FPGA as the core controller, We adopt Verilog HDL and top-down design method to build a top-level module design and also analyze the mark logic of asynchronous FIFO and the elimination of semi-stable state under Quartus II development platform. Besides, with the application of Gray code conversion technology, not only the reliable transmission of data is guaranteed but also design efficiency is improved. Through contrast experiment analysis and simulation test, the validity and reliability of asynchronous FIFO memory are verified, meeting the basic requirement that FIFO can hold more enough data without spillovers despite the fullness of data. |
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Bibliography: | Selected, peer reviewed papers from the 2014 International Conference on Machine Tool Technology and Mechatronics Engineering (ICMTTME 2014), June 22-23, 2014, Guilin, Guangxi, China |
ISBN: | 9783038352464 3038352462 |
ISSN: | 1660-9336 1662-7482 1662-7482 |
DOI: | 10.4028/www.scientific.net/AMM.644-650.3440 |