Plasma-Enhanced Atomic Layer Deposition-Based Ferroelectric Field-Effect Transistors

• Published in: IEEE journal of the Electron Devices Society Vol. 12; pp. 569 - 572
• Main Authors: Park, Chinsung, Ravindran, Prasanna Venkat, Das, Dipjyoti, Ravikumar, Priyankka Gundlapudi, Zhang, Chengyang, Afroze, Nashrah, Fernandes, Lance, Kuo, Yu Hsin, Hur, Jae, Chen, Hang, Tian, Mengkun, Chern, Winston, Yu, Shimeng, Khan, Asif Islam
• Format: Journal Article
• Language: English
• Published: New York IEEE 2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Atomic layer deposition; Atomic layer epitaxy; Current measurement; Electric potential; FEFET; FeFETs; Ferroelectric materials; Ferroelectricity; Field effect transistors; Logic gates; memory window; plasma-enhanced atomic layer deposition; Plasmas; Semiconductor devices; Silicon dioxide; thermal atomic layer deposition; Transistors; Voltage; Voltage measurement
• ISSN: 2168-6734; 2168-6734
• DOI: 10.1109/JEDS.2024.3434598

The use of the plasma-enhanced atomic layer deposition (ALD) technique for the deposition of HfO2-based ferroelectrics has received attention in recent years primarily due to wake-up free operation. However, these studies have primarily focused on metal-ferroelectric-metal (MFM) structures. In this work, we investigate the characteristics of ferroelectric field-effect transistors (FEFETs) in which the ferroelectric Hf0.5Zr0.5O2 (HZO) gate stack is deposited using the plasma-enhanced atomic layer deposition (PEALD) technique. We observe that PEALD FEFET requires a higher write voltage for the same memory window compared to an equivalent FEFET with thermal ALD (THALD)-grown HZO. The increase in write voltage in PEALD FEFET occurs primarily due to the increase of the interfacial oxide layer using the plasma process. In addition, we observe that the SiO2 interfacial layer underneath the ferroelectric (FE) HZO layer eliminates the wake-up behavior in both THALD and PEALD FEFETs.