Short-circuit energy dissipation modeling for submicrometer CMOS gates

• Published in: IEEE transactions on circuits and systems. 1, Fundamental theory and applications Vol. 47; no. 9; pp. 1350 - 1361
• Main Authors: Bisdounis, L., Koufopavlou, O.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2000; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analytical models; Capacitance; Circuit simulation; Energy dissipation; Inverters; MOSFETs; Power dissipation; Semiconductor device modeling; SPICE; Very large scale integration
• ISSN: 1057-7122; 1558-1268
• DOI: 10.1109/81.883330

A significant part of the energy dissipation in static complementary metal-oxide-semiconductor (CMOS) structures is due to short-circuit currents. In this paper, an accurate analytical model for the CMOS short-circuit energy dissipation is presented. First, the short-circuit energy dissipation of the CMOS inverter is modeled. The derived model is based on analytical expressions of the inverter output waveform which include the influences of both transistor currents and the gate-to-drain coupling capacitance. Also, the effect of the short-circuiting transistor's gate-source capacitance on the short-circuit energy dissipation, is taken into account. The /spl alpha/-power law MOS model that considers the carriers' velocity saturation effect of submicrometer devices is used. Second, the inverter model is extended to static CMOS gates by using reduction techniques of series- and parallel-connected transistors. The results produced by the suggested model for a commercial 0.8-/spl mu/m process, show very good agreement with SPICE simulations.