Nanostructural Investigation on GaAs//Indium Tin Oxide/Si Junctions for III-V-on-Si Hybrid Multijunction Cells

• Published in: ECS transactions Vol. 98; no. 4; pp. 125 - 133
• Main Authors: Hara, Tomoya, Liang, Jianbo, Araki, Kenji, Kamioka, Takefumi, Sodabanlu, Hassanet, Watanabe, Kentaroh, Sugiyama, Masakazu, Shigekawa, Naoteru
• Format: Journal Article
• Language: English
• Published: The Electrochemical Society, Inc 08.09.2020
• ISSN: 1938-5862; 1938-6737
• DOI: 10.1149/09804.0125ecst

We investigate nanostructural properties of GaAs//indium tin oxide (ITO)/Si junctions fabricated by surface-activated bonding with emphasis on impacts of thermal process. Both of the Ga 2p3/2 and As 2p3/2 core-level spectra obtained by hard X-ray photoemission spectroscopy show that the GaAs layers are oxidized by annealing at 400℃. This finding is consistent with the formation of amorphous-like layers at 400℃ annealed GaAs//ITO interfaces. Concentration depth profiles of O, Ga, and As suggest that the oxidation markedly occurs at GaAs//ITO interfaces annealed at temperatures higher than 200℃, which is consistent with the dependence of resistance in GaAs//ITO/Si junctions on annealing temperature. These results suggest that annealing brings about the reaction between GaAs and ITO layers and causes the degradation of the electrical properties of GaAs//ITO interfaces. Low-temperature process technologies are essential so as to make a full use of ITO as intermediate layers in III-V-on-Si multijunction cells.