Runtime-Aware Architectures
In the last few years, the traditional ways to keep the increase of hardware performance to the rate predicted by the Moore’s Law have vanished. When uni-cores were the norm, hardware design was decoupled from the software stack thanks to a well defined Instruction Set Architecture (ISA). This simpl...
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Published in | Euro-Par 2015: Parallel Processing pp. 16 - 27 |
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Main Authors | , , , , , , , , , , , , |
Format | Book Chapter Publication |
Language | English |
Published |
Berlin, Heidelberg
Springer Berlin Heidelberg
2015
Springer |
Series | Lecture Notes in Computer Science |
Subjects | |
Online Access | Get full text |
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Summary: | In the last few years, the traditional ways to keep the increase of hardware performance to the rate predicted by the Moore’s Law have vanished. When uni-cores were the norm, hardware design was decoupled from the software stack thanks to a well defined Instruction Set Architecture (ISA). This simple interface allowed developing applications without worrying too much about the underlying hardware, while hardware designers were able to aggressively exploit instruction-level parallelism (ILP) in superscalar processors. Current multi-cores are designed as simple symmetric multiprocessors (SMP) on a chip. However, we believe that this is not enough to overcome all the problems that multi-cores face. The runtime system of the parallel programming model has to drive the design of future multi-cores to overcome the restrictions in terms of power, memory, programmability and resilience that multi-cores have. In the paper, we introduce an approach towards a Runtime-Aware Architecture (RAA), a massively parallel architecture designed from the runtime’s perspective. |
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ISBN: | 9783662480953 3662480956 3662480964 9783662480960 |
ISSN: | 0302-9743 1611-3349 |
DOI: | 10.1007/978-3-662-48096-0_2 |