Low-cost FPGA implementation of 2D digital pre-distorter for concurrent dual-band power amplifier

This paper proposes a low-cost hardware architecture based on concurrent dual-band digital pre-distorter （DPD）. The architecture is implemented on field programmable gate array （FPGA） to compensate for the nonlinearity of the concurrent dual-band power amplifier （PA）. This implementation introduces...

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Bibliographic Details
Published inJournal of China universities of posts and telecommunications Vol. 23; no. 1; pp. 14 - 21
Main Authors Guang, Zeng, Cuiping, Yu, Shulan, Li, Yuan'an, Liu
Format Journal Article
LanguageEnglish
Published Elsevier Ltd 01.02.2016
Subjects
Channels
concurrent dual-band
Data buses
Digital
digital predistorter
field programmable gate array (FPGA)
Field programmable gate arrays
FPGA
Hardware
lookup table
Lookup tables
power amplifier
Power amplifiers
Sidebands
低成本
功率放大器
双波段
并发
现场可编程门阵列
维数
预失真器
power amplifier
concurrent dual-band
field programmable gate array (FPGA)
digital predistorter
lookup table
Online AccessGet full text
ISSN1005-8885
DOI10.1016/S1005-8885(16)60003-1

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Summary:This paper proposes a low-cost hardware architecture based on concurrent dual-band digital pre-distorter （DPD）. The architecture is implemented on field programmable gate array （FPGA） to compensate for the nonlinearity of the concurrent dual-band power amplifier （PA）. This implementation introduces a novel model complexity reduction technique into system, namely, time-division multiplexing for out-of-band lookup tables （LUTs） sharing. Performances are evaluated with an experimental test setup using a wideband class-F PA. The dual-band signal center frequency separated by 80 MHz. Lower and upper center frequency are located at 2.61 GHz and 2.69 GHz, respectively. This novel DPD implementation maintains excellent performance, but uses hardware resources reduced by 29.17% compared with conventional approaches. The results show that the adjacent channel power ratio （ACPR） is less than -59 dBc and normalized mean square error （NMSE） is around - 62dB for lower sideband （LSB） and - 63dB for upper sideband （USB）.
Bibliography:11-3486/TN
power amplifier, concurrent dual-band, digital predistorter, lookup table, field programmable gate array （FPGA）
This paper proposes a low-cost hardware architecture based on concurrent dual-band digital pre-distorter （DPD）. The architecture is implemented on field programmable gate array （FPGA） to compensate for the nonlinearity of the concurrent dual-band power amplifier （PA）. This implementation introduces a novel model complexity reduction technique into system, namely, time-division multiplexing for out-of-band lookup tables （LUTs） sharing. Performances are evaluated with an experimental test setup using a wideband class-F PA. The dual-band signal center frequency separated by 80 MHz. Lower and upper center frequency are located at 2.61 GHz and 2.69 GHz, respectively. This novel DPD implementation maintains excellent performance, but uses hardware resources reduced by 29.17% compared with conventional approaches. The results show that the adjacent channel power ratio （ACPR） is less than -59 dBc and normalized mean square error （NMSE） is around - 62dB for lower sideband （LSB） and - 63dB for upper sideband （USB）.
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ISSN:1005-8885
DOI:10.1016/S1005-8885(16)60003-1