A 3-10 GHz CMOS UWB Low-Noise Amplifier With ESD Protection Circuits

• Published in: IEEE microwave and wireless components letters Vol. 19; no. 11; pp. 737 - 739
• Main Authors: WU, Chung-Yu, LO, Yi-Kai, CHEN, Min-Chiao
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.11.2009; Institute of Electrical and Electronics Engineers
• Subjects: Amplifiers; Applied sciences; Circuit properties; Circuits; CMOS; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Electrostatic discharge; electrostatic discharge (ESD); Exact sciences and technology; Gain measurement; Impedance matching; Integrated circuits; low-noise amplifier (LNA); Low-noise amplifiers; Noise figure; Noise measurement; Power measurement; Protection; Semiconductor device measurement; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; ultra-wide band (UWB); Noise figure; Low noise circuit; Circuit design; Return loss; Power gain; Low noise amplifier; Electrostatic discharge; ultra-wide band (UWB); Protection circuit; Ultra wide band; CMOS; low-noise amplifier (LNA); Power consumption; Integrated circuit testing; Energy dissipation; Complementary MOS technology; Electric power consumption; Robustness; Low-power electronics; electrostatic discharge (ESD)
• ISSN: 1531-1309; 1558-1764
• DOI: 10.1109/LMWC.2009.2032022

A low-power fully integrated low-noise amplifier (LNA) with an on-chip electrostatic-static discharge (ESD) protection circuit for ultra-wide band (UWB) applications is presented. With the use of a common-gate scheme with a g m -boosted technique, a simple input matching network, low noise figure (NF), and low power consumption can be achieved. Through the combination of an input matching network, an ESD clamp circuit has been designed for the proposed LNA circuit to enhance system robustness. The measured results show that the fabricated LNA can be operated over the full UWB bandwidth of 3.0 to 10.35 GHz. The input return loss (S 11 ) and output return loss (S 22 ) are less than -8.3 dB and -9 dB, respectively. The measured power gain (S21) is 11 plusmn1.5 dB, and the measured minimum NF is 3.3 dB at 4 GHz. The dc power dissipation is 7.2 mW from a 1.2 V supply. The chip area, including testing pads, is 1.05 mm times 0.73 mm.