Detailed study of NBTI characterization in 40-nm CMOS process using comprehensive models

The impact of negative bias temperature instability （NBTI） can be ascribed to three mutually uncorrelated factors, including hole trapping by pre-existing traps （△ VHT） in gate insulator, generated traps （△ VOT） in bulk insulator, and interface trap generation （△ VIT）. In this paper, we have experim...

Full description

Saved in:
Bibliographic Details
Published inChinese physics B Vol. 26; no. 10; pp. 483 - 489
Main Author 曾严 李小进 卿健 孙亚宾 石艳玲 郭奥 胡少坚
Format Journal Article
LanguageEnglish
Published 01.10.2017
Subjects
CMOS
互补金属氧化物半导体
反应扩散模型
工艺线
恢复特性
界面陷阱
综合模型
负偏压温度
Online AccessGet full text

Cover

More Information
Summary:The impact of negative bias temperature instability （NBTI） can be ascribed to three mutually uncorrelated factors, including hole trapping by pre-existing traps （△ VHT） in gate insulator, generated traps （△ VOT） in bulk insulator, and interface trap generation （△ VIT）. In this paper, we have experimentally investigated the NBTI characteristic for a 40-nm complementary metal-oxide semiconductor （CMOS） process. The power-law time dependence, temperature activation, and field acceleration have also been explored based on the physical reaction-diffusion model. Moreover, the end-of-life of stressed device dependent on the variation of stress field and temperature have been evaluated. With the consideration of locking effect, the recovery characteristics have been modelled and discussed.
Bibliography:negative bias temperature instability （NBTI）, reaction diffusion （RD）, interface trap, H2 locking effect
Yan Zeng1, Xiao-Jin Li1, Jian Qing1, Ya-Bin Sun1, Yan-Ling Shi1, Ao Guo2, Shao-Jian Hu2（1 Shanghai Key Laboratory of Multidimensional Information Processing and Department of Electrical Engineering, East China Normal University, Shanghai 200241, China ; 2Shanghai Integrated Circuit Research ＆ Development Center, Shanghai 201203, China）
The impact of negative bias temperature instability （NBTI） can be ascribed to three mutually uncorrelated factors, including hole trapping by pre-existing traps （△ VHT） in gate insulator, generated traps （△ VOT） in bulk insulator, and interface trap generation （△ VIT）. In this paper, we have experimentally investigated the NBTI characteristic for a 40-nm complementary metal-oxide semiconductor （CMOS） process. The power-law time dependence, temperature activation, and field acceleration have also been explored based on the physical reaction-diffusion model. Moreover, the end-of-life of stressed device dependent on the variation of stress field and temperature have been evaluated. With the consideration of locking effect, the recovery characteristics have been modelled and discussed.
11-5639/O4
ISSN:1674-1056
2058-3834
DOI:10.1088/1674-1056/26/10/108503