An analog front end with a 12-bit 3.2-MS/s SAR ADC for a power line communication system

This paper presents an analog front end for a power line communication system, including a 12-bit 3.2-MS/s energy-efficient successive approximation register analog-to-digital converter, a positive feedback programmable gain amplifier, a 9.8 ppm/℃ bandgap reference and on-chip low-output voltage reg...

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Bibliographic Details
Published inJournal of semiconductors Vol. 35; no. 11; pp. 141 - 148
Main Author 陈华斌 向济璇 薛香艳 陈迟晓 叶凡 许俊 任俊彦
Format Journal Article
LanguageEnglish
Published 01.11.2014
Subjects
ADC
SAR
可编程增益放大器
模拟前端
电力线通信系统
节约成本
通讯系统
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Summary:This paper presents an analog front end for a power line communication system, including a 12-bit 3.2-MS/s energy-efficient successive approximation register analog-to-digital converter, a positive feedback programmable gain amplifier, a 9.8 ppm/℃ bandgap reference and on-chip low-output voltage regulators. A two segment capacitive array structure （6 MSB 5 LSB） composed by split capacitors is designed for the SAR core to save area cost and release reference voltage accuracy requirements. Implemented in the GSMC 0.13 #m 1.5 V/12 V dual-gate 4P6M e-flash process, the analog front end occupies an area of 0.457 mm2 and consumes power of 18.8 mW, in which 1.1 mW cost by the SAR ADC. Measured at 500 kHz input, the spurious-free dynamic range and signal-to-noise plus distortion ratio of the ADC are 71.57 dB and 60.60 dB respectively, achieving a figure of merit of 350 U/conversion-step.
Bibliography:This paper presents an analog front end for a power line communication system, including a 12-bit 3.2-MS/s energy-efficient successive approximation register analog-to-digital converter, a positive feedback programmable gain amplifier, a 9.8 ppm/℃ bandgap reference and on-chip low-output voltage regulators. A two segment capacitive array structure （6 MSB 5 LSB） composed by split capacitors is designed for the SAR core to save area cost and release reference voltage accuracy requirements. Implemented in the GSMC 0.13 #m 1.5 V/12 V dual-gate 4P6M e-flash process, the analog front end occupies an area of 0.457 mm2 and consumes power of 18.8 mW, in which 1.1 mW cost by the SAR ADC. Measured at 500 kHz input, the spurious-free dynamic range and signal-to-noise plus distortion ratio of the ADC are 71.57 dB and 60.60 dB respectively, achieving a figure of merit of 350 U/conversion-step.
analog front end; successive approximation register; A/D; power line communication
11-5781/TN
Chen Huabin, Xiang Jixuan, Xue Xiangyan, Chen Chixiao, Ye Fan, Xu Jun, Ren Junyan（State-Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China）
ISSN:1674-4926
DOI:10.1088/1674-4926/35/11/115008