An ultrafast front-end ASIC for APD array detectors in X-ray time-resolved experiments

An ultrafast front-end ASIC chip has been developed for APD array detectors in X-ray time-resolved experiments. The chip has five channels: four complete channels and one test channel with an analog output. Each complete channel consists of a preamplifier, a voltage discriminator and an open-drain o...

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Bibliographic Details
Published inChinese physics C Vol. 41; no. 6; pp. 134 - 141
Main Author 周杨帆 李秋菊 刘鹏 樊磊 徐伟 陶冶 李贞杰
Format Journal Article
LanguageEnglish
Published 01.06.2017
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Summary:An ultrafast front-end ASIC chip has been developed for APD array detectors in X-ray time-resolved experiments. The chip has five channels: four complete channels and one test channel with an analog output. Each complete channel consists of a preamplifier, a voltage discriminator and an open-drain output driver. A prototype chip has been designed and fabricated using 0.13 μm CMOS technology with a chip size of 1.3 mm×1.9 mm. The electrical characterizations of the circuit demonstrate a very good intrinsic time resolution(rms) on the output pulse leading edge, with the test result better than 30 ps for high input signal charges(〉 75 fC) and better than 100 ps for low input signal charges(30-75 fC), while keeping a low power consumption of 5 mW per complete channel.
Bibliography:11-5641/O4
time-resolved, APD, ASIC, synchrotron X-ray
Yang-Fan Zhou1,Qiu-Ju Li1, Peng Liu1, Lei Fan2 , Wei Xu1, Ye Tao1, Zhen-Jie Li1(1 Beijing Synchrotron Radiation Facility, Institute of High Energy Physics, Chinese Academy of Sciences, Beijing 100049, China; 2 State Key Laboratory of Particle Detection and Electronics, Institute of High Energy Physics, Chinese Academy of Sciences, Beijing 100049, China)
An ultrafast front-end ASIC chip has been developed for APD array detectors in X-ray time-resolved experiments. The chip has five channels: four complete channels and one test channel with an analog output. Each complete channel consists of a preamplifier, a voltage discriminator and an open-drain output driver. A prototype chip has been designed and fabricated using 0.13 μm CMOS technology with a chip size of 1.3 mm×1.9 mm. The electrical characterizations of the circuit demonstrate a very good intrinsic time resolution(rms) on the output pulse leading edge, with the test result better than 30 ps for high input signal charges(〉 75 fC) and better than 100 ps for low input signal charges(30-75 fC), while keeping a low power consumption of 5 mW per complete channel.
ISSN:1674-1137
0254-3052
DOI:10.1088/1674-1137/41/6/066101