Efficient Implementation of Single Error Correction and Double Error Detection Code with Check Bit Pre-computation for Memories

• Published in: Journal of semiconductor technology and science Vol. 12; no. 4; pp. 418 - 425
• Main Authors: Cha, Sanguhn, Yoon, Hongil
• Format: Journal Article
• Language: English
• Published: 대한전자공학회 01.12.2012
• Subjects: 전기공학
• ISSN: 1598-1657; 2233-4866
• DOI: 10.5573/JSTS.2012.12.4.418

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit precomputation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weightcolumn code during the write operation and is designed by replacing 0’s with 1’s at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the oddweight-column code, the implementation based on the proposed SEC-DED code with check bit precomputation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1%for 64 data bits in a word. KCI Citation Count: 7