High- \kappa/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length

• Published in: IEEE electron device letters Vol. 31; no. 4; pp. 275 - 277
• Main Authors: Khater, M.H., Zhen Zhang, Jin Cai, Lavoie, C., D'Emic, C., Qingyun Yang, Bin Yang, Guillorn, M., Klaus, D., Ott, J.A., Yu Zhu, Ying Zhang, Changhwan Choi, Frank, M.M., Kam-Leung Lee, Narayanan, V., Dae-Gyu Park, Qiqing Ouyang, Haensch, W.
• Format: Journal Article
• Language: English
• Published: IEEE 01.04.2010
• Subjects: Annealing; CMOS; CMOS process; CMOS technology; Depletion; Devices; Drains; Extremely thin SOI (ETSOI); Fabrication; Gates; high- kappa /metal-gate CMOS; Implants; Inorganic materials; Intermetallics; MOSFETs; NiPt silicide; Parasitic capacitance; Schottky barrier (SB) lowering; Schottky barriers; Schottky source/drain (S/D); Silicides
• ISSN: 0741-3106; 1558-0563; 1558-0563
• DOI: 10.1109/LED.2010.2040133

Schottky source/drain (S/D) MOSFETs hold the promise for low series resistance and extremely abrupt junctions, providing a path for device scaling in conjunction with a low Schottky barrier height (SBH). A S/D junction SBH approaching zero is also needed to achieve a competitive current drive. In this letter, we demonstrate a CMOS process flow that accomplishes a reduction of the S/D SBH for nFET and pFET simultaneously using implants into a common NiPt silicide, followed by a low-temperature anneal (500°C-600°C). These devices have high-κ/metal gate and fully depleted extremely thin SOI with sub-30-nm gate length.