Constrained via minimization for three-layer routing

• Published in: Computer aided design Vol. 21; no. 6; pp. 346 - 354
• Main Authors: Chang, K.E., Jyu, H.F., Feng, W.S.
• Format: Journal Article
• Language: English
• Published: Oxford Elsevier Ltd 01.07.1989; Elsevier Science
• Subjects: Applied sciences; computer-aided design; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; graph contractibility; Integrated circuits; layer assignment; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; via minimization; VLSI design; via minimization; computer-aided design; VLSI design; graph contractibility; layer assignment; VLSI circuit; Interconnection; Integrated circuit; Heuristic method; Minimization; NP complete problem; Chromatic graph; Graph method; Computer aid; Computer aided design; Multilayered circuit; Constrained optimization
• ISSN: 0010-4485; 1879-2685
• DOI: 10.1016/0010-4485(89)90001-8

The constrained via minimization problem for VLSI three-layer routing is the problem of determining which layers can be used for routing the wire segments in the interconnections of nets so that the number of vias is minimized. This problem has been shown to be NP-complete 15. In this paper, this problem is first transformed to the contractibility problem of a three-colourable graph, then an heuristic algorithm is proposed on the basis of the graph contractability model. From experimental results, the algorithm proves faster and more efficient at generating very good results. For a typical case, the number of vias can be reduced by about 30%.