A mathematical formulation to design and implementation of a low voltage swing transceiver circuit

• Published in: Integration (Amsterdam) Vol. 58; pp. 356 - 368
• Main Authors: Mondal, Abir J., Majumder, Alak, Bhattacharyya, Bidyut K.
• Format: Journal Article
• Language: English
• Published: Amsterdam Elsevier B.V 01.06.2017; Elsevier BV
• Subjects: Circuit design; CMOS; Comparator; Computer simulation; Crosstalk; Current sources; Data transfer (computers); Frequencies; Ground plane; Leakage current; Low voltage; Low voltage swing; Pulse duration; Signaling; Studies; Switching; Threshold voltage; Transceivers; Transmitters; Threshold voltage; Leakage current; Current sources; Low voltage swing; Crosstalk; Comparator
• ISSN: 0167-9260; 1872-7522
• DOI: 10.1016/j.vlsi.2016.11.013

On switching a transmitter at gigahertz rate, the data at the receiver's end gets distorted in terms of pulse width and voltage due to line loss and dispersion originating from channel electrical characteristics. Signalling using current sources is an established approach for high frequency applications, but different receiver circuits have been proposed to effectively sense the low voltage swings around some reference voltage, VT. At first, the VT is identified at the receiver's input by a unique method and the corresponding value is found to be 0.822V. Thereafter, a signalling scheme has been proposed to have two different current sources capable of generating a low voltage swing around VT at the receiver's end and at the same time compensating the line loss of the channel. The low voltage swings around VT cause leakage current to increase. The proposed methodology reduces the constant short circuit current due to low voltage swings around VT almost close to 0 from 56μA for 60mV swing. The PVT analyses of the VT determination circuit and the proposed signalling scheme indicate the sensitivity of the proposed approach while operated at 1GHz switching frequency. Further, the crosstalk analysis for a 60mV swing around VT at 180nm CMOS process and single ended point to point drivers portrays that the desired s/h (s is the edge to edge space between two traces and h is the corresponding height from the ground plane) has to be greater than 2.3 for crosstalk noise to be below the critical value. Measurements and simulations also indicate that the proposed methodology for terminated design consumes only 1.08mW for data transfer over point to point interconnects compared to conventional schemes. •A unique signalling scheme made up of two different current sources have been proposed and analysed so as to imitate signal attenuation originating from channel loss.•At first, the minimum swing required for the CMOS gates at the receiver to switch state is determined.•Thereafter, mathematical relations are developed for the proposed current mode signalling scheme in order to generate low voltage swing at receiver's input.•Further, the proposed current mode signalling circuit serves as a basis to determine the desired VT against which low voltage swing needs to be generated•It is also observed that the generation of low voltage swing around VT at the input of a CMOS gate results in leakage current•To prevent leakage current a methodology consisting of two extra gates and an additional clock is introduced. The clock arrives before the data depending on the maximum data rate.•Lastly, the effect of crosstalk for a 60mV swing around VT at 180nm technology and for single ended point to point driver is observed.•It is noted that the design parameter s/h should be greater than 2.3 for 50Ω characteristic impedance of channel when terminated with 50Ω resistance.