Interactive Two-Dimensional Design of Barrier-Controlled MOS Transistors

• Published in: IEEE journal of solid-state circuits Vol. 15; no. 4; pp. 615 - 623
• Main Authors: Liu, S., Hoefflinger, B., Pederson, D.O.
• Format: Journal Article
• Language: English
• Published: IEEE 01.08.1980
• Subjects: Circuit simulation; Computer displays; Doping; Geometry; Graphics; Impurities; MOSFETs; Three dimensional displays; Threshold voltage; Two dimensional displays
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.1980.1051445

An interactive program has been developed for the graphic generation and the solution of two-dimensional impurity, earner, potential, and field distributions in small-geometry MOS transistor configurations. Emphasis is placed on conversational operation and three-dimensional display on a graphics terminal with a generation rate, for any self-consistent two-dimensional solution, of less than few minutes for each computation and drawing. Although this limited the approach to a solution of the potential problem only, the barrier-controlled characteristics in weak inversion and weak injection (punch-through) are produced efficiently and provide quantitative data for slopes, threshold voltages, and punch through voltages, as well as their two-dimensional dependence on device geometry, doping, and terminal voltages. Examples are presented for NMOS transistors with various enhancement and buried channel implants. The program is useful both as a pre-selector for structures to be simulated with a more elaborate two-dmensional potential and transport program and as a generator of parameters for a device model in a circuit simulator.