Significant improvement of 45 nm and beyond complementary metal oxide semiconductor field effect transistor performance with fully silicided and ultimate spacer process technology

• Published in: Thin solid films Vol. 516; no. 21; pp. 7741 - 7743
• Main Authors: Hsu, Chia-Wei, Fang, Yean-Kuen, Lin, Chien-Ting, Yeh, Wen-Kuan, Hsu, Che-Hua, Lai, Chieh-Ming, Cheng, Li-Wei, Ma, Mike
• Format: Journal Article
• Language: English
• Published: Lausanne Elsevier B.V 01.09.2008; Elsevier Science
• Subjects: Applied sciences; Electronics; Exact sciences and technology; Fully silicided metal gate; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Strain engineering; Transistors; Ultimate spacer process; Fully silicided metal gate; Ultimate spacer process; Strain engineering; MOSFET; Compressive stress; Tensile stress; Silicides; Spacer; Stress effects; Gates
• ISSN: 0040-6090; 1879-2731
• DOI: 10.1016/j.tsf.2008.04.064

A fully silicided (FUSI) metal gate process is merged with ultimate spacer process (USP) strain engineering to effectively enhance the performances of deep nano complementary metal oxide semiconductor field effect transistor (CMOSFET). Using the merged FUSI–USP process, the FUSI gate can be processed with the source/drain region silicide in one step, and the poly gate can be thinned to less than 300 Å, thus shortening the distance between the strain contact etch stop layer and the channel to generate higher stress. Therefore, I on gain up to 28% can be achieved in an n type MOSFET with tensile-stress, and 40% in a p type MOSFET with compressive-stress.