A 400 Mb/s∼2.5 Gb/s Referenceless CDR IC Using Intrinsic Frequency Detection Capability of Half-Rate Linear Phase Detector

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 63; no. 10; pp. 1592 - 1604
• Main Author: Byun, Sangjin
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.10.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Clock and data recovery; Clocks; CMOS integrated circuits; Detectors; frequency detection; Integrated circuits; Iterative closest point algorithm; linear phase detector; Phase frequency detector; Timing
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2016.2587751

A 400 Mb/s ~2.5 Gb/s referenceless clock and data recovery (CDR) IC is presented. This paper shows that the half-rate linear phase detector (PD) has not only phase detection capability but also single-sided frequency detection capability in itself. By using this intrinsic frequency detection capability of the half-rate linear PD, a CDR can be implemented in the single loop architecture without both an external reference clock and a separate frequency detector. For verification, a prototype CDR IC was fabricated in a 0.13 μm CMOS process. With 2.5 Gb/s, 2 31 - 1 pseudorandom binary sequence (PRBS), the measurement results show that the frequency acquisition time is 17 μs, the bit error rate (BER) is better than 10 -12 , the jitter of the recovered clock is 8.6 psrms and the out-of-band jitter tolerance is 0.32 UI pp .