Advantages of LDD-only implanted fluorine with submicron CMOS technologies

• Published in: IEEE transactions on electron devices Vol. 44; no. 3; pp. 388 - 394
• Main Authors: Mogul, H.C., Rost, T.A., Der-Gao Lin
• Format: Journal Article
• Language: English
• Published: IEEE 01.03.1997
• Subjects: Application specific processors; CMOS process; CMOS technology; Implants; Instruments; Interface states; Light emitting diodes; Testing; Threshold voltage; Vehicles
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/16.556148

The effect of fluorine implantation on the properties of shallow n/sup +//p junctions has been investigated. The novel approach of this work lies in the introduction of fluorine only in the LDD regions of the device and not in the active region underneath the gate. Gated diodes were used as test vehicles to study the effect of the fluorine incorporation. Gated diodes are ideal for measurements of this nature since they are sensitive to changes in the interfacial properties near the gate to diffusion overlap region. Results from electrical device characterization indicate a reduction in gated diode leakage and mid-gap interface state density as the F-implanted dose is increased without causing any significant change in the flat-band voltages. Results also showed that samples with F incorporation tended to be more robust to electrical stress than those without F. Materials analysis indicated reduced junction depths for samples with F introduced in the LDD regions indicating suppression of phosphorus dopant diffusion.