CMOS microsensor packaging for use in aqueous media

• Published in: Journal of micromechanics and microengineering Vol. 35; no. 7; pp. 75003 - 75015
• Main Authors: Dobroliubov, O, Kakati, A, Stokke, B T, Häfliger, P, Johannessen, E A
• Format: Journal Article
• Language: English
• Published: IOP Publishing 31.07.2025
• Subjects: aqueous environment; CMOS; microfabrication; packaging; polymer sealants
• ISSN: 0960-1317; 1361-6439
• DOI: 10.1088/1361-6439/ade3e5

Industrial standards for direct packaging of complementary metal oxide semiconductor (CMOS) microelectronic silicon chips exist as hermetically sealed packages for medical, commercial, military and space applications, with some equipped with a channel for use as sensors in gas/vacuum. Yet none exist for direct access to aqueous (wet) environments, and home-made makeshift solutions prevail. Facing this challenge, a protocol that enables reliable packaging of microelectronic chips exposed to aqueous environments exemplified with eight different polymer sealing materials have been developed. Chips coated with Si 3 N 4 or SiO 2 —common CMOS materials—were applied in combination with a novel microfabricated silicon frame acting as a flow stop barrier which enabled backfilling without compromising the active area for chips as small as 1 × 1 mm 2 . Photocurable resins that can be patterned directly were used for comparison. Tests were conducted in biological equivalent saline solution at 57 °C representing an accelerated testing regime of 14× compared to that found at 20 °C and 4× compared to 37 °C. Although the results highlighted a significant degree of individual variation, it was found that silicones were able to protect the chip structures up to the duration of the testing regime (960 h/40 d). The epoxies in general suffered from a more rapid decline and lasted up to 35–40 h (approx. 1.5 d) with the acrylates in between (60–85 h/2.5–3.5 d). In contrast, silicones subject to autoclavation at 134 °C (30 psi, 2 bar) for 3 min exhibited a survival rate of only 16%. There were no discernible differences between chips surfaces made from Si 3 N 4 or SiO 2 .