Compatibility of Dielectric Passivation and Temporary Bonding Materials for Thin Wafer Handling in 3-D TSV Integration

• Published in: IEEE transactions on components, packaging, and manufacturing technology (2011) Vol. 1; no. 12; pp. 1988 - 1995
• Main Authors: Jaesik Lee, Seetoh, J., Hong Yu Li, Lee, V., Yen Chen Yeo, Guan Kian Lau, Keng Hwa Teo, Shan Gao
• Format: Journal Article
• Language: English
• Published: Piscataway, NJ IEEE 01.12.2011; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 3-D integration; Applied sciences; Bonding; Copper; Design. Technologies. Operation analysis. Testing; Dielectrics; Electronics; Exact sciences and technology; Heat treatment; Integrated circuits; Materials; microbump; Passivation; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; temporary bonding and de-bonding; thin wafer handling; through silicon via; Through-silicon vias; microbump; thin wafer handling; Dielectric materials; Analyzer; Integrated circuit bonding; Hardening; Back surface; Scanning microscope; temporary bonding and de-bonding; Solder bump; Three dimensional structure; through silicon via; Interconnection; Acoustic microscopy; Integrated circuit; Silicon; Void; Wafer; Passivation; Via hole; 3-D integration
• ISSN: 2156-3950; 2156-3985
• DOI: 10.1109/TCPMT.2011.2162435

The effects of temporary bonding processes on thin wafer handling were investigated. Backside dielectric curing process was found to be a critical process for the void formation in the thin wafer handling which was confirmed by scanning acoustic microscope and by thermo-gravimetric analyzer out-gassing analysis. The effects of voids on back-side wafer processes were discussed. Finally, 3-D through silicon via integration with thin wafer handling (50 μm in thickness) was demonstrated with selected dielectric passivation material and temporary bonding adhesives.