Design of GGNMOS ESD protection device for radiation-hardened 0.18 μm CMOS process
In this paper, the ESD discharge capability of GGNMOS (gate grounded NMOS) device in the radiation-hardened 0.18 μm bulk silicon CMOS process (Rad-Hard by Process: RHBP) is optimized by layout and ion implantation design. The effects of gate length, DCGS and ESD ion implantation of GGNMOS on dischar...
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Published in | Journal of semiconductors Vol. 41; no. 12; pp. 122403 - 59 |
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Main Authors | , , , |
Format | Journal Article |
Language | English |
Published |
Chinese Institute of Electronics
01.12.2020
The 58th Research Institute of China Electronics Technology Group Corporation,Wuxi 214035,China |
Subjects | |
Online Access | Get full text |
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Summary: | In this paper, the ESD discharge capability of GGNMOS (gate grounded NMOS) device in the radiation-hardened 0.18 μm bulk silicon CMOS process (Rad-Hard by Process: RHBP) is optimized by layout and ion implantation design. The effects of gate length, DCGS and ESD ion implantation of GGNMOS on discharge current density and lattice temperature are studied by TCAD and device simulation. The size of DCGS, multi finger number and single finger width of ESD verification structures are designed, and the discharge capacity and efficiency of GGNMOS devices in ESD are characterized by TLP test technology. Finally, the optimized GGNMOS is verified on the DSP circuit, and its ESD performance is over 3500 V in HBM mode. |
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ISSN: | 1674-4926 2058-6140 |
DOI: | 10.1088/1674-4926/41/12/122403 |