Optimizing resource utilization using transformations

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 13; no. 3; pp. 277 - 292
• Main Authors: Potkonjak, M., Rabaey, J.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.03.1994; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Clocks; Constraint optimization; Cost function; Delay; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; High level synthesis; IIR filters; Integrated circuits; Iterative algorithms; Processor scheduling; Resource management; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Timing; Experimental result; Probabilistic approach; Integrated circuit; Optimization method; Theoretical study; Circuit synthesis; Custom circuit; Real time system; Computer aided design
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/43.265670

The goal of the high level synthesis process for real time applications is to minimize the implementation cost, while still satisfying all timing constraints. In this paper, the authors present a combination of four conceptually simple, yet powerful, transformations: namely retiming, associativity, commutativity and inverse element law, which can help to further this goal. Since the minimization problem associated with these transformations is NP complete, a new fast iterative improvement probabilistic algorithm has been developed. The effectiveness of the proposed algorithm and the associated transformations is demonstrated in multiple ways: using standard benchmark examples, with the aid of statistical analysis and through a comparison with estimated minimal bounds.< >