A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation

A 16-Mb flash EEPROM has been developed based on the 0.6-/spl mu/m triple-well double-poly-Si single-metal CMOS technology. A compact row decoder circuit for a negative gate biased erase operation has been designed to obtain the sector erase operation. A self-data-refresh scheme has been developed t...

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 29; no. 4; pp. 461 - 469
Main Authors Atsumi, S., Kuriyama, M., Umezawa, A., Banba, H., Naruke, K., Yamada, S., Ohshima, Y., Oshikiri, M., Hiura, Y., Yamane, T., Yoshikawa, K.
Format Journal Article
LanguageEnglish
Published IEEE 01.04.1994
Subjects
Circuits
Decoding
EPROM
Flash memory
Laboratories
Semiconductor devices
Semiconductor diodes
Temperature
Threshold voltage
Voltage control
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Summary:A 16-Mb flash EEPROM has been developed based on the 0.6-/spl mu/m triple-well double-poly-Si single-metal CMOS technology. A compact row decoder circuit for a negative gate biased erase operation has been designed to obtain the sector erase operation. A self-data-refresh scheme has been developed to overcome the drain-disturb problem for unselected sector cells. A self-convergence method after erasure is applied in this device to overcome the overerase problem that causes read operation failure. Both the self-data-refresh operation and the self-convergence method are verified to be involved in the autoerase operation. Internal voltage generators independent of the external voltage supply and temperature has been developed. The cell size is 2.0 /spl mu/m/spl times/1.7 /spl mu/m, resulting in a die size of 7.7 mm/spl times/17.32 mm.< >
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0018-9200
1558-173X
DOI:10.1109/4.280696