Pinch-Off Plasma CVD Deposition Process and Material Technology for Nano-Device Air Gap/Spacer Formation

• Published in: ECS transactions Vol. 85; no. 6; pp. 25 - 39
• Main Authors: Nguyen, Son van, Haigh, Thomas J, Cheng, Kangguo, Penny, C., Park, Chanro, Li, J., Mehta, Sanjay C, Yamashita, Tenko, Jiang, Liying, Canaperi, Don
• Format: Journal Article
• Language: English
• Published: The Electrochemical Society, Inc 09.04.2018
• ISSN: 1938-5862; 1938-6737; 1938-6737; 1938-5862
• DOI: 10.1149/08506.0025ecst

As integrated circuits for high performance CMOS devices scale down to ≤ 10 nm dimension, further reductions in capacitance are vitally important for device performance. It is important to reduce capacitance in the FEOL and BEOL device structures while maintaining fabrication integration robustness. This paper presents an overview of material and process technology requirements for FEOL air spacer (1) and BEOL air gap (2) formation using a pinch-off deposition approach. These approaches utilize established dielectric materials and processes such as Plasma CVD of SiN, SiCN, SiCOH, pSiCOH, in the formation of the air spacer/air gap. The selection of these dielectric materials and processes has a large impact in the void (gap) dimension and volume. The void dimension and volume in airgap/air spacer structures can be controlled with various dielectric deposition processes and materials to facilitate subsequent process fabrication steps, and ultimately to build a robust device with substantial capacitance reduction.