(Invited) Extending Advanced CMOS Scaling with SiGe Channel Materials

• Published in: ECS transactions Vol. 85; no. 6; pp. 3 - 10
• Main Authors: Carter, Rick J, Sporer, Ryan, McArdle, Timothy J, Mulfinger, George Robert, Holt, Judson Robert, Beasor, Scott, Child, Amy, Fronheiser, Jody, Wahl, Jeremy A, Geisler, Holm, Kluth, George J, Triyoso, Dina H, Punchihewa, Kasun, Rana, Uzma, Vanamurthy, Laks, Sohn, D K
• Format: Journal Article
• Language: English
• Published: The Electrochemical Society, Inc 09.04.2018
• ISSN: 1938-5862; 1938-6737; 1938-6737; 1938-5862
• DOI: 10.1149/08506.0003ecst

Advanced CMOS Scaling has benefited from the introduction of novel materials and integration techniques over the past two decades. Consumer demand for more connectivity and real-time information continues to drive the need for product solutions with advanced power management and increased functionality while maintaining low cost. New device architectures such as FINFET and Fully Depleted Silicon-On-Insulator are part of the solution, however these device architectures still rely on advanced channel strain engineering to meet power, performance, and scaling requirements. The use of SiGe as a channel material is attractive due to enhanced mobility and compatibility with standard CMOS processing. PFET drive current enhancement has already been realized to enable platforms based on high performance planar FDSOI devices, while SiGe as part of the channel is also a top solution to enable next generation FINFET and Gate-All-Around devices. In this invited paper we will provide a look into the device benefits and challenges of SiGe as a channel material.