A flexible VLSI architecture of transport processor for an AVS HDTV decoder SoC

• Published in: IEEE transactions on consumer electronics Vol. 52; no. 4; pp. 1427 - 1432
• Main Authors: Zhang, Zhenrui, Wu, Di, Zhang, Peng, Xie, Don, Gao, Wen
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2006; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Acceleration; Architecture; Broadcasting; Circuit simulation; Decoders; Decoding; Design engineering; Hardware design languages; HDTV; Integrated circuits; IPTV; Microprocessors; Process design; Reduced instruction set computing; Simulation; Transport; Very large scale integration
• ISSN: 0098-3063; 1558-4127
• DOI: 10.1109/TCE.2006.273166

In this paper, we present a VLSI design of transport processor for an AVS HDTV decoder SoC. The design provides a flexible data flow, which supports both broadcasting service and IPTV service with DVR capability. The design is characterized by two-bus architecture, in which a RISC CPU is used for control of general purpose and some dedicated hardware for accelerating data processing. The common on-chip SRAM is used to store input transport packets and the intermediate result in order to improve system performance and reduce the area. The design is described in Verilog HDL, simulated with VCS simulator, and implemented using 0.18 mum CMOS cell library. The circuit costs about 75 k equivalent logic gates and the processing capability is up to 90 Mbps