Scan design at NEC

• Published in: IEEE design & test of computers Vol. 6; no. 3; pp. 50 - 51
• Main Authors: Funatsu, S., Kawai, M., Yamada, A.
• Format: Journal Article
• Language: English
• Published: IEEE Computer Society 01.06.1989
• Subjects: Automatic testing; Circuit faults; Circuit testing; Costs; Flip-flops; Logic testing; National electric code; System testing; Test pattern generators; Very large scale integration

The authors describe scan path, NEC's implementation of the scan design approach to design for testability. Designers at NEC have found that scan path greatly contributes to the reduced testing and maintenance cost of their products. The authors discuss several implementations of scan design an...