Scan design at NEC

The authors describe scan path, NEC's implementation of the scan design approach to design for testability. Designers at NEC have found that scan path greatly contributes to the reduced testing and maintenance cost of their products. The authors discuss several implementations of scan design an...

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Bibliographic Details
Published inIEEE design & test of computers Vol. 6; no. 3; pp. 50 - 51
Main Authors Funatsu, S., Kawai, M., Yamada, A.
Format Journal Article
LanguageEnglish
Published IEEE Computer Society 01.06.1989
Subjects
Automatic testing
Circuit faults
Circuit testing
Costs
Flip-flops
Logic testing
National electric code
System testing
Test pattern generators
Very large scale integration
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Summary:The authors describe scan path, NEC's implementation of the scan design approach to design for testability. Designers at NEC have found that scan path greatly contributes to the reduced testing and maintenance cost of their products. The authors discuss several implementations of scan design and compare four implementations, including two scan-path techniques.< >
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0740-7475
1558-1918
DOI:10.1109/54.32412