Low-Power Single Bitline Load Sense Amplifier for DRAM

• Published in: Electronics (Basel) Vol. 12; no. 19; p. 4024
• Main Authors: Dai, Chenghu, Lu, Yixiao, Lu, Wenjuan, Lin, Zhiting, Wu, Xiulong, Peng, Chunyu
• Format: Journal Article
• Language: English
• Published: Basel MDPI AG 01.10.2023
• Subjects: Arrays; Circuits; Discharge; Dynamic random access memory; Electric potential; Energy consumption; Integrated circuits; Power management; Random access memory; Sense amplifiers; Transistors; Very large scale integration; Voltage
• ISSN: 2079-9292; 2079-9292
• DOI: 10.3390/electronics12194024

With the significant growth in modern computing systems, dynamic random access memory (DRAM) has become a power/performance/energy bottleneck in data-intensive applications. Both the power management mechanism and downscaling method face decreasing performance or difficulties in the smaller footprint of the DRAM capacitor. Since optimizing the circuit of sense amplifier (SA) is an efficient method to reduce energy consumption, we propose two single bitline load sense amplifier (SBLSA) circuits, i.e., a redundant voltage discharged SBLSA (RVD-SBLSA) circuit and a bit aware SBLSA (BA-SBLSA) circuit, to improve conventional and single bitline write (SBW) circuits. The RVD-SBLSA circuit utilizes a clamp diode to discharge redundant voltage over VDD/2 with an additional working stage. The BA-SBLSA circuit abandons the single bitline load (SBL) circuit during read and write ‘1’ operations. The RVD-SBLSA circuit can offer the lowest total energy consumption, and the BA-SBLSA circuit can make a better balance between energy consumption and latency. Through the simulation results, the proposed circuits can efficiently reduce energy consumption or balance energy consumption and latency and show huge potentials in very large-scale integrated circuits.