A 28-Gbps Radix-16, 512-Point FFT Processor-Based Continuous Streaming OFDM for WiGig

• Published in: Circuits, systems, and signal processing Vol. 41; no. 5; pp. 2871 - 2897
• Main Authors: Agarwal, Sumit, Ahamed, Shaik Rafi, Gogoi, Anup, Trivedi, Gaurav
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.05.2022; Springer Nature B.V
• Subjects: Circuit design; Circuits and Systems; Computer architecture; Continuous flow; Electrical Engineering; Electronics and Microelectronics; Engineering; Fast Fourier transformations; Fourier transforms; Instrumentation; Local area networks; Microprocessors; Signal,Image and Speech Processing; Switching circuits; FFT processor; ASIC; Wireless HD; WLAN; FFT chip
• ISSN: 0278-081X; 1531-5878
• DOI: 10.1007/s00034-021-01917-0

A fast Fourier transform (FFT) chip for IEEE 802.11ay wireless local area network (WLAN) standard has to stream at 20–40 Gbps with a continuous flow (CF). The earlier WLAN standard, IEEE 802.11ad, had a throughput of 7–10 Gbps. In order to double the throughput, the processing elements and memories would need to be increased, thus drastically increasing the area. The proposed 512-point radix 16 FFT architecture achieves 28-Gbps throughput occupying only 20% more chip area than the best existing 10–15-Gbps designs. Apart from that, it has all three capabilities: CF, conflict-free access (CFA), and normal order input–output. Most FFTs use two memories in a switched fashion for CF. This design uses an additional smaller input memory by exploiting the smaller wordlength of 4 bit (for 64 QAM) of OFDM. Three memories are dedicated individually to the three stages of the FFT. This architecture necessitates the development of a new technique of CF, which replaces data in memory rather than switching the memories. Substantial savings are realized by removing memory switching. Also, a simplified CFA is proposed, which further saves area. These innovations help to cut down area from switching circuits and lead to a lower complexity design. The design fabricated in SCL technology in a 120-pin package meets the 4.8 Gsps (28 Gbps) processing rate at a clock speed of 300 MHz.