Design and implementation of optimized 2D FIR symmetric filter architecture using modified McClellan transformation and CSD-CSE

In this paper, an optimized and high-performance Two Dimensional-Finite Impulse Response (2D-FIR) filter is designed and hardware architecture is implemented for real-time image processing applications. The higher-order circular symmetric 2D-FIR filter is designed using a modified McClellan Transfor...

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Bibliographic Details
Published inMultidimensional systems and signal processing Vol. 36; no. 1
Main Authors Odugu, Venkata Krishna, Rao, Bitra Janardhana, Bojjawar, Satish, Raju, U. Appala
Format Journal Article
LanguageEnglish
Published New York Springer US 01.12.2025
Springer Nature B.V
Subjects
Artificial Intelligence
Circuits and Systems
Delay
Design
Electrical Engineering
Engineering
FIR filters
Image filters
Image processing
Impulse response
Real time
Signal,Image and Speech Processing
2D FIR filter
CSE
Multiplierless design CSD
McClellan transformation
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Summary:In this paper, an optimized and high-performance Two Dimensional-Finite Impulse Response (2D-FIR) filter is designed and hardware architecture is implemented for real-time image processing applications. The higher-order circular symmetric 2D-FIR filter is designed using a modified McClellan Transformation a P4 transformation. The designed filter coefficients are represented by the Canonical Signed Digit (CSD) number format to attain the multiplierless design. Further, the Common Subexpression Elimination (CSE) technique is utilized to reduce the number of adders of the CSD-based 2D-FIR filter architecture. The Fully Direct Form (FDF) structure is considered to implement the proposed architecture. The designed 2D-FIR FDF architecture is coded by HDL according to the structure and synthesized by Cadence tools in a 45 nm CMOS technology library. The Delay, Power, and Area reports were generated by the Genus synthesis tool and compared with the state-of-the-art works. Significant improvements are observed in the proposed 2D filter architecture. The proposed 2D-FIR filter architecture has a decreased maximum of 10.48 times and a minimum of 1.18 times of Area Delay Product (ADP), as well as a decreased maximum of 10.69 times and a minimum of 1.063 times of Power Delay Product (PDP).
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ISSN:0923-6082
1573-0824
DOI:10.1007/s11045-024-00895-1