Analysis and efficient implementation of IEEE-754 decimal floating point adders/subtractors in FPGAs for DPD and BID encoding

• Published in: The Journal of supercomputing Vol. 80; no. 7; pp. 9298 - 9326
• Main Authors: Tosini, Marcelo, Vázquez, Martín, Leiva, Lucas
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.05.2024; Springer Nature B.V
• Subjects: Coding; Compilers; Computation; Computer Science; Field programmable gate arrays; Floating point arithmetic; Interpreters; Processor Architectures; Programming Languages; Subtraction; Floating-point representation; FPGA; Decimal arithmetic
• ISSN: 0920-8542; 1573-0484
• DOI: 10.1007/s11227-023-05808-w

This paper proposes efficient implementations for addition/subtraction based on decimal floating point with Densely Packed Decimal (DPD) and Binary Integer Decimal (BID) encoding in FPGA devices. The designs use novel techniques based on the efficient utilization of dedicated resources in programmable devices. Implementations were made in Xilinx UltraScale+. For DPD adder/subtractor, they have computation times of 7.7 ns for Decimal32 , 8.1 ns for Decimal64 and 8.5 ns for Decimal128 . As for BID adder/subtractor, the computation time obtained is 13.5 ns for Decimal64 . The proposed architecture achieves better computation times than related works. Compared to previous architectures, the proposed DPD implementation achieves 1.86 × speedup and 47% better LUT occupation. Also, the BID adder/subtractor achieves 3 × speedup and 5% less LUT occupation.