Area and Power Efficient AVLS-TSPC-Based Diffused Bit Generator for Key Generation

The diffused bit generator (DBG) is an entropy generator that generates a stream of random bits. DBG is realized using a linear feedback shift register (LFSR) and cellular automata (CA). LFSR and CA are realized using flip-flops and XOR gates. The flip-flops required are designed using true single-p...

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Bibliographic Details
Published inCircuits, systems, and signal processing Vol. 43; no. 5; pp. 3102 - 3117
Main Authors Premananda, B. S., Rehman, Abdur, Megha, P.
Format Journal Article
LanguageEnglish
Published New York Springer US 01.05.2024
Springer Nature B.V
Subjects
Cellular automata
Circuits
Circuits and Systems
CMOS
Electric potential
Electrical Engineering
Electronics and Microelectronics
Energy dissipation
Engineering
Flip-flops
Gates (circuits)
Instrumentation
Linear feedback shift registers
Power consumption
Signal,Image and Speech Processing
Transistors
Voltage
DBG
AVLS
LFSR
Cryptography
TSPC
CA
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Summary:The diffused bit generator (DBG) is an entropy generator that generates a stream of random bits. DBG is realized using a linear feedback shift register (LFSR) and cellular automata (CA). LFSR and CA are realized using flip-flops and XOR gates. The flip-flops required are designed using true single-phase clock (TSPC)-based logic to minimize the area and power of the LFSR and CA circuits. The XOR gates used in the circuits are realized either using a 12-transistor (12T) or a 6-transistor (6T). To further reduce power dissipation in the DBG circuit, low-power techniques are incorporated. In the proposed 8-bit DBGs, the adaptive voltage level at source (AVLS) is incorporated to reduce power consumption. The circuits are realized using Cadence Virtuoso in CMOS 180 nm technology, and Specter is used for simulation and power analysis. The DBG functionality is assessed for frequencies ranging up to 1 GHz with a supply voltage of 1.8 V. From the results, it was inferred that at 1 GHz the proposed-1 DBG (using a 12T XOR gate) is 94.05% power efficient; while, the proposed-2 DBG (using a 6T XOR gate) is 90.27% power efficient when compared to the reference circuits. Implementation of the proposed-1 DBG was also carried out in CMOS 45 nm technology, the functionality was verified and the power was analyzed. A similar trend of power reduction was observed.
ISSN:0278-081X
1531-5878
DOI:10.1007/s00034-023-02596-9