High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors

• Published in: Journal of electronic testing Vol. 36; no. 1; pp. 87 - 103
• Main Authors: Oyeniran, Adeboye Stephen, Ubar, Raimund, Jenihhin, Maksim, Raik, Jaan
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.02.2020; Springer Nature B.V
• Subjects: CAE) and Design; Circuits and Systems; Computer simulation; Computer-Aided Engineering (CAD; Electrical Engineering; Engineering; Fault detection; Microprocessors; Processors; RISC; Software; High-level control fault model; Processor testing; Functional test generation; Fault simulation; Low-level fault redundancy; High-level fault coverage
• ISSN: 0923-8174; 1573-0727
• DOI: 10.1007/s10836-020-05856-7

The paper proposes a novel high-level approach for implementation-independent generation of functional software-based self test programs for processors with RISC architectures. The approach enables fast generation of manufacturing tests with high stuck-at fault coverage. The main concept of the method is based on separate test generation for the control and data parts of the high-level functional units. For the control part, a novel high-level control fault model is introduced whereas for the data part, pseudo-exhaustive test approaches can be applied to keep the independence from the implementation details. For the control parts, a novel high-level fault simulation method is proposed for evaluating the high-level fault coverage. The approach can be used for easy identification of redundant gate-level faults in the control part. The redundant faults can be identified by simple gate-level fault simulation of the generated high-level test when implementation is available. Experimental results of test generation for different units of a RISC processor support the solutions presented in the paper.