A Two's Complement Array Multiplier Using True Values of the Operands

A new algorithm for implementing the two's complement multiplication of an m × n bit number is described. By interpreting certain positive partial product bits as negative, a parallel array is developed which has the advantage of using only one type of adder cell. A comparison with the Pezaris...

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Bibliographic Details
Published inIEEE transactions on computers Vol. C-32; no. 8; pp. 745 - 747
Main Authors BANDEIRA, N, VACCARO, K, HOWARD, J. A
Format Journal Article
LanguageEnglish
Published New York, NY IEEE 01.08.1983
Institute of Electrical and Electronics Engineers
Subjects
Algorithmics. Computability. Computer arithmetics
Applied sciences
Array multiplier
Baugh-Wooley multiplier
binary multiplication
celluar-subtractor multiplier
Computer science; control theory; systems
Exact sciences and technology
parallel multiplier
Pezaris multiplier
Theoretical computing
Computers arithmetic
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Summary:A new algorithm for implementing the two's complement multiplication of an m × n bit number is described. By interpreting certain positive partial product bits as negative, a parallel array is developed which has the advantage of using only one type of adder cell. A comparison with the Pezaris and Baugh-Wooley arrays is presented, showing that the new array is as fast as the Pezaris array and uses less hardware than the Baugh-Wooley implementation.
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.1983.1676312